The present invention relates to an electronic digital circuit, and more particularly to a circuit for synchronizing asynchronous high speed data to a system clock in order to use the high speed data in an electronic data processing system.
High speed electronic data processing systems often are required to receive and assimilate high speed data signals that are asynchronous with respect to the internal clock of the system. For example, data signals received via a proposed IEEE X3T9.2 (SCSI II) bus or an FDDI bus. A known data synchronizer uses a type of AND gate to sample the asynchronous data signals at a data input with an edge (either leading or trailing) of the system clock pulse. Each sample is, therefore, the binary product of the asynchronous input signal level and the clock edge level. Additionally, each binary product is subsequently stored in a flip-flop until it is synchronously read by the remainder of the receiving system.
A common problem in this known type of data synchronizer is the occurrence of metastable oscillations. Metastable oscillations occur in cross coupled feedback devices, such as flip-flops, when the set up times of their inputs have not been observed. The set-up time requirement is essentially the time required for the two inputs of a cross coupled feedback device to switch to a stable binary condition. Unfortunately with asynchronous inputs, proper set-up times cannot be assured.
One solution to this problem is to precede the cross coupled device with a sampling gate such as an AND gate or a NAND gate. The asynchronous data signal is inputted on one of the AND/NAND inputs and a second input is driven by the sampling clock. The AND/NAND gate pre conditions the asynchronous signal to the system clock and removes some of the metastability problem. However, there is still a metastability problem when the asynchronous input signal is changing binary states at the same time that the system clock is sampling the asynchronous input signal. In such a case, the resulting product of the AND/NAND gate may be a signal having an intermediate level that is too high to be considered a binary LO state, and too low to be considered a binary HI state. Such an intermediate signal level may be considered by binary devices as either a HI state or a LO state. On the other hand, the resulting output of the AND/NAND pre-conditioner may be a signal that is too brief in duration to provide sufficient time for the input gates of the cross coupled device to reliably switch to a stable condition that would be logically required by the input pulse if it had sufficient duration. Thus, the known synchronizer with an AND/NAND pre-conditioner is less prone to metastability problems, but they still occur.
Thus, there is a need in the art for a synchronizer which overcomes metastability problems. Such a synchronizer would use a method of synchronizing an asynchronous input that would be applicable to all logic families and fabrication processes as long as the characteristics of each logic family and fabrication process were observed.
It is an object of the present invention to provide a data synchronizer that is free from metastable oscillations.
It is another object of the invention to provide a data synchronizer that operates at a high clock frequencies and high asynchronous data rates without metastability problems.